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www.irf.com 1 1/16/04 irf3709z irf3709zs irf3709zl hexfet power mosfet notes through are on page 12 applications benefits low r ds(on) at 4.5v v gs low gate charge fully characterized avalanche voltage and current high frequency synchronous buck converters for computer processor power v dss r ds(on) max qg 30v 6.3m 17nc d 2 pak irf3709zs to-220ab irf3709z to-262 irf3709zl absolute maximum ratin g s parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v a i d @ t c = 100c continuous drain current, v gs @ 10v i dm pulsed drain current p d @t c = 25c maximum power dissipation w p d @t c = 100c maximum power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds mounting torque, 6-32 or m3 screw thermal resistance parameter typ. max. units r jc junction-to-case CCC 1.89 c/w r ja junction-to-ambient (pcb mount) CCC 40 300 (1.6mm from case) -55 to + 175 10 lbf in (1.1n m) 79 0.53 40 max. 87 62 350 20 30 downloaded from: http:///

2 www.irf.com s d g static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 30 CCC CCC v ? v dss / ? t j breakdown voltage temp. coefficient CCC 0.021 CCC mv/c r ds(on) static drain-to-source on-resistance CCC 5.0 6.3 m ? CCC 6.2 7.8 v gs(th) gate threshold voltage 1.35 CCC 2.25 v ? v gs(th) / ? t j gate threshold voltage coefficient CCC -5.5 CCC mv/c i dss drain-to-source leakage current CCC CCC 1.0 a CCC CCC 150 i gss gate-to-source forward leakage CCC CCC 100 na gate-to-source reverse leakage CCC CCC -100 gfs forward transconductance 88 CCC CCC s q g total gate charge CCC 17 26 q gs1 pre-vth gate-to-source charge CCC 4.4 CCC q gs2 post-vth gate-to-source charge CCC 1.7 CCC nc q gd gate-to-drain charge CCC 6.0 CCC q godr gate charge overdrive CCC 4.9 CCC see fig. 14a&b q sw switch charge (q gs2 + q gd ) CCC 7.7 CCC q oss output charge CCC 11 CCC nc t d(on) turn-on delay time CCC 13 CCC t r rise time CCC 41 CCC t d(off) turn-off delay time CCC 16 CCC ns t f fall time CCC 4.7 CCC c iss input capacitance CCC 2130 CCC c oss output capacitance CCC 450 CCC pf c rss reverse transfer capacitance CCC 220 CCC avalanche characteristics parameter units e as single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj diode characteristics parameter min. typ. max. units i s continuous source current CCC CCC 87 (body diode) a i sm pulsed source current CCC CCC 350 (body diode) v sd diode forward voltage CCC CCC 1.0 v t rr reverse recovery time CCC 16 24 ns q rr reverse recovery charge CCC 6.2 9.3 nc mosfet symbol v gs = 4.5v, i d = 17a CCC v gs = 4.5v typ. CCCCCC i d = 17a v gs = 0v v ds = 15v t j = 25c, i f = 17a, v dd = 15v di/dt = 100a/s t j = 25c, i s = 17a, v gs = 0v showing the integral reverse p-n junction diode. v ds = v gs , i d = 250a v ds = 24v, v gs = 0v v ds = 24v, v gs = 0v, t j = 125c clamped inductive load v ds = 15v, i d = 17a v ds = 16v, v gs = 0v v dd = 15v, v gs = 4.5v i d = 17a v ds = 15v conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 21a v gs = 20v v gs = -20v conditions 7.9 max. 6017 ? = 1.0mhz downloaded from: http:///

www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 3.0v 60s pulse width tj = 175c vgs top 10v 9.0v 7.0v 5.0v 4.5v 4.0v 3.5v bottom 3.0v 0.1 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 10v 9.0v 7.0v 5.0v 4.5v 4.0v 3.5v bottom 3.0v 60s pulse width tj = 25c 3.0v 0 1 2 3 4 5 6 7 8 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) t j = 25c t j = 175c v ds = 15v 60s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 42a v gs = 10v downloaded from: http:///

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 5 10 15 20 25 q g total gate charge (nc) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 24v v ds = 15v i d = 17a 0.0 0.5 1.0 1.5 2.0 2.5 v sd , source-to-drain voltage (v) 1.00 10.00 100.00 1000.00 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 0 1 10 100 1000 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 1msec 10msec operation in this area limited by r ds (on) 100sec tc = 25c tj = 175c single pulse downloaded from: http:///

www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. threshold voltage vs. temperature 25 50 75 100 125 150 175 t c , case temperature (c) 0 10 20 30 40 50 60 70 80 90 i d , d r a i n c u r r e n t ( a ) limited by package -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 0.5 1.0 1.5 2.0 2.5 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.832 0.0002211.058 0.001171 j j 1 1 2 2 r 1 r 1 r 2 r 2 c ci i / ri ci= i / ri downloaded from: http:///

6 www.irf.com fig 13. on-resistance vs. gate voltage fig 12. on-resistance vs. drain current fig 16. maximum avalanche energy vs. drain current fig 14a&b. basic gate charge test circuit and waveform fig 15a&b. unclamped inductive test circuit and waveforms t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - vds vgs id vgs(th) qgs1 qgs2 qgd qgodr 2 3 4 5 6 7 8 9 10 v gs, gate -to -source voltage (v) 0 2 4 6 8 10 12 14 16 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ? ) i d = 21a t j = 25c t j = 125c 10.0 20.0 30.0 40.0 50.0 60.0 70.0 i d , drain current (a) 4.00 5.00 6.00 7.00 8.00 9.00 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ? ) t j = 25c t j = 125c vgs = 10v 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 5.4a 8.0a bottom 17a downloaded from: http:///

www.irf.com 7 fig 17.
for n-channel hexfet power mosfets
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? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period

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8 www.irf.com control fet

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#' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f ? ? ? ? ? ? + q g v g f () + q oss 2 v in f ? ? ? ? " (

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synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f ( ) *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be-tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca-pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic downloaded from: http:///

www.irf.com 9

dimensions are shown in millimeters (inches) lead assignments 1 - gate 2 - drain 3 - source 4 - drain - b - 1.32 (.052) 1.22 (.048) 3x 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 4.69 (.185) 4.20 (.165) 3x 0.93 (.037) 0.69 (.027) 4.06 (.160) 3.55 (.140) 1.15 (.045) min 6.47 (.255) 6.10 (.240) 3.78 (.149) 3.54 (.139) - a - 10.54 (.415) 10.29 (.405) 2.87 (.113) 2.62 (.103) 15.24 (.600) 14.84 (.584) 14.09 (.555) 13.47 (.530) 3x 1.40 (.055) 1.15 (.045) 2.54 (.100) 2x 0.36 (.014) m b a m 4 1 2 3 notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 3 outline conforms to jedec outline to-220ab. 2 controlling dimension : inch 4 heatsink & lead measurements do n ot include burrs. hexfet 1- gate 2- drain 3- source 4- drain lead assignments igbts, copack 1- gate 2- collector 3- emitter 4- collector

note: "p" in assembly line position indicates "lead-free" downloaded from: http:///

10 www.irf.com

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dimensions are shown in millimeters (inches) downloaded from: http:///

www.irf.com 11 to-262 package outlinedimensions are shown in millimeters (inches) to-262 part marking information

igbt 1- gate2- collec- tor downloaded from: http:///

12 www.irf.com data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 01/04
repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 0.42mh, r g = 25 ? , i as = 17a. pulse width 400s; duty cycle 2%. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . this is applied to d 2 pak, when mounted on 1" square pcb (fr- 4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. calculated continuous current based on maximum allowable junction temperature. package limitation current is 42a. r is measured at

dimensions are shown in millimeters (inches) 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) max. 27.40 (1.079) 23.90 (.941) 60.00 (2.362) min. 30.40 (1.197) max. 26.40 (1.039) 24.40 (.961) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. downloaded from: http:///
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:///

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